Analysis and Design of Resilient VLSI Circuits: Mitigating - download pdf or read online

By Rajesh Garg

ISBN-10: 1441909303

ISBN-13: 9781441909305

This publication is stimulated through the demanding situations confronted in designing trustworthy integratedsystems utilizing sleek VLSI techniques. The trustworthy operation of built-in Circuits (ICs) has turn into more and more tricky to accomplish within the deep sub-micron (DSM) period. With constantly reducing equipment characteristic sizes, mixed with reduce offer voltages and better working frequencies, the noise immunity of VLSI circuits is lowering alarmingly. hence, VLSI circuits have gotten extra liable to noise results equivalent to crosstalk, energy offer diversifications and radiation-induced delicate errors.

This ebook describes the layout of resilient VLSI circuits. It provides algorithms to investigate the hazardous results of radiation particle moves and processing diversifications at the electric habit of VLSI circuits, in addition to circuit layout suggestions to mitigate the effect of those problems.

  • Describes the cutting-edge within the parts of radiation tolerant circuit layout and technique edition tolerant circuit design;
  • Presents analytical techniques to check successfully the severity of electric results of radiation/process adaptations, in addition to innovations to reduce the consequences because of those problems;
  • Distills content material orientated towards nuclear engineers into modern algorithms and methods that may be understood simply and utilized by way of VLSI designers.

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Additional resources for Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations

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3 Proposed Analytical Model for the Pulse Width of Radiation-induced Voltage Glitch 25 PTM [7] model card with VDD D 1 V. The radiation-induced transient are classified into four cases, in Sect. 2. The proposed model for the pulse width computation, based on these cases, is introduced in Sect. 3. 4 provides the derivation of the expression for the pulse width of the radiation-induced voltage glitch. 1 Radiation Particle Strike at the Output of an Inverter Consider an inverter INV1 driving three identical inverters as shown in Fig.

A. S. thesis, Vanderbilt University, 2006. 22. S. S. thesis, Vanderbilt University, 2008. 23. G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, pp. 1–4, April 1965. 24. R. E. Kessler, “The Alpha 21264 microprocessor,” IEEE Micro, vol. 19, no. 2, pp. 24–36, 1999. 25. H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spatial correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp.

The model is applicable to any logic gate, with arbitrary gate size and loading, and with different amounts of charge collected due to the radiation strike. The model can be used to quickly (1,000 faster than SPICE [38]) determine the susceptible gates in a design (the gates where a radiation particle strike can result in a voltage glitch with a positive pulse width). The most susceptible gates can then be protected using circuit hardening approaches, based on the degree of hardening desired. In Chap.

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Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations by Rajesh Garg

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